According to Moore's Law, the number of transistors per silicon chip doubles every 18 months, and the sizes of devices decrease in proportion to a factor of approximately 0.7 every three years.
Larger wafers hold more chips and can reduce per-chip cost. 300 mm wafers are now commonly used in semiconductor manufacturing processes and the industry is pushing for an even larger wafer size of 450 mm in diameter.
Although the wafers having large sizes, such as 300 mm, 450 mm, or even larger, can be used to reduce manufacturing cost, larger wafers introduce new issues that were not previously considered in smaller wafers. One critical issue is the wafer warpage which has become more severe with 300 mm or larger wafers.
Wafer warpage causes many undesired manufacturing defects. For example, a spun-on layer on the wafer may have a larger thickness at the centre than the outer edge. In an etching process, critical dimension (CD) uniformity problem from wafer center to edge at least partly comes from imperfect chucking over wafer warpage. And in a photolithographic process, a photoresist (PR) layer's thickness uniformity from wafer centre to outer edge is critical. During exposure, wafer warpage induced focus drift can be disastrous for CD uniformity. An electrostatic chuck (also referred to as ESC or e-chuck) is often employed to solve the problem of wafer warpage in the semiconductor manufacturing process.
However, an electrostatic chuck often suffers from chucking uniformity and particle contamination while performing a flattening process on the wafer. Therefore, there is a need to provide methods for avoiding undesired effects in wafer chucking.